The use of switching regulators to control a DC output voltage at a level higher than, lower than, or the same as an input voltage is well known. Typically, one or more switches are activated to supply current pulses via an inductor to charge an output capacitor. The output voltage level is maintained at a desired level by adjusting the on and off times of the switching pulses in accordance with output voltage and load conditions. When there is an abrupt change in load conditions, the controller may not be able to react sufficiently to prevent an output voltage overshoot that exceeds specification tolerances. For example, a load may suddenly be changed from maximum current operation to low current usage; the regulator may continue to output high current to increase the output voltage before responding sufficiently to the changed condition.
In many portable systems, when the output load is light, the switching regulators are controlled to go into a power saving sleep mode. In the sleep mode, the regulator reduces the operating current by turning off some internal circuitry while operating in a burst mode. In this burst mode, the regulator output is initially higher than the programmed level and the internal circuitry is turned off to save power consumption. Due to the output load, the output voltage then drifts lower to the programmed level and the regulator wakes up and turns on the internal circuitry to drive the output higher to repeat cycles. Output overshoot occurs when the regulator wakes up to drive the output high due to the regulator loop response delay.
FIG. 1 is a block diagram of a typical current mode switching regulator. Switching control circuit 10 may comprise any of various known controllers that provide pulse width modulated output pulses to regulate a DC output voltage VOUT at a level that may be greater than, lower than, or the same as a nominal input voltage VIN. Typically, the control circuit includes a latch, having set and reset inputs, coupled to a controlled switch that supplies switched current ISW to inductor 12. Capacitor 14 is connected between the output VOUT and ground. Resistors 16 and 18 are connected in series between VOUT and ground. A load 20 is supplied from the regulator output.
The set input is coupled to clock 22, which may generate pulses in response to an oscillator, not shown. During the normal or “wake” mode operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator 24. An output voltage feedback signal VFB is taken at the junction of resistors 16 and 18 and coupled to negative input of error amplifier 26. A voltage reference VREF is applied to the positive input of error amplifier 26. Capacitor 28 is coupled between the output of error amplifier 26 and ground.
The level of charge of capacitor 28, and thus its voltage VC, is varied in dependence upon the output of amplifier 26. As load current increases, the output voltage, and thus VFB, decreases. As the feedback voltage VFB decreases, VC increases. Thus, VC is proportional to load current. VC is coupled to the inverting input of comparator 24. The non-inverting input is coupled to a signal ISW proportional to the sensed switch current. Upon switch activation in response to a clock set signal, switch current builds through inductor 12. When the level of ISW exceeds VC, comparator 24 generates a reset signal to terminate the switched current pulse. During heavier loads VC increases and the switched current pulse accordingly increases to appropriately regulate the output voltage VOUT.
When there is a sudden change in load conditions from high level load current to very low level load current, the system loop response time can be insufficient to prevent the output voltage from exceeding maximum voltage specification. The output voltage quickly decreases due to the high current draw and VC rises sharply. The switch current pulse width, responsive to the reset signal output of comparator 24, increases, driving the output voltage higher. Output voltage overshoot may exist until VC can adjust to the appropriate level.
During light load conditions, VOUT tends to increase and thus VC decreases. The switched current pulse width decreases. Internal circuitry, not shown, detects VC and changes the mode of operation to “sleep mode” when VC falls to a preset level, which is significantly lower than normal wake mode level. Operation returns to the “wake mode.” At the initiation of the “wake mode,” clock signals received at the set input again activates switching. The switched current pulses can cause output voltage overshoot before VC can adjust to the appropriate level.
FIG. 2 is a block diagram of a prior art arrangement for limiting voltage output overshoot. OR gate 30 is coupled between the output of comparator 24 and reset input of control circuit 10. Comparator 32 comprises a non-inverting input coupled to feedback signal VFB and an inverting input coupled to a set reference voltage VREF1. The output of comparator 32 is coupled to the OR gate 30. The OR gate will output a reset signal when either comparator 24 or 32 outputs a high logic level. The voltage level VREF1 is set to a level corresponding to a programmed level of overshoot, for example, at eight to ten percent higher than VREF. When VFB rises to VREF1, a reset signal will be generated by the comparator 32 through OR gate 30. Comparator 32 thus can be considered to be an over voltage protection comparator. The initiation of the overshoot reset is independent of VC. During the reset condition imposed by comparator 32, no current pulses are produced. VOUT decreases and VC adjusts accordingly.
The threshold VREF1 must be set high enough to accommodate the worst case of high ripple at heavy load during normal operation. As ripple does not contribute to DC voltage output, nor adversely affect the load, the threshold is set to permit operation with high ripple. In burst mode, in the transition from the sleep mode, however, because the load is light, the ripple is generally significantly less than heavy load ripple. Since VREF1 has been set to a level matched to high ripple, when the comparator 32 is activated to reset in the transition from sleep mode, a detrimental output voltage overshoot will already have occurred. For example, at heavy load during normal operation, VC may correspond to one volt. VREF1 has been designed to accommodate the ripple occurring from load change operation from an initial VC value of one volt. In the sleep mode, VC may typically correspond to one-half volt. At the transition to wake mode, VOUT already is at or near maximum level. With relatively light load at normal operation, the current pulses will drive VOUT higher, with considerably less ripple. VREF1 is not low enough to prevent undesirable overshoot during the time in which VC appropriate adjusts.
The need thus exists for improved over voltage protection in switched regulator circuits.